1. Field of the Invention
The present invention relates to a ferroelectric memory and, more particularly, to a data read circuit for reading out data that were written to ferroelectric capacitors.
2. Description of the Related Art
Recently, a ferroelectric memory reading method called “bitline GND sensing method” has been proposed (IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, pp. 592–597, May 2002 and Japanese Unexamined Patent Application Publication No. 2002-133857).
FIG. 1 shows the main part of a ferroelectric memory that employs the conventional bit-line GND sensing method. A memory cell array ARY has memory cells MC called “2T2C cells” and column switches CSW. To hold 1-bit information, each 2T2C cell is composed of two transfer transistors and two ferroelectric capacitors FC. One end of each ferroelectric capacitor FC is connected to a bit line BL or XBL via the associated transfer transistor and the other end is connected to a plate line PL. The gate of each transfer transistor is connected to a word line WL. Symbol Cbl denotes the capacitance of each bit line. The column switches CSW connect the bit lines BL and XBL to data bus lines in response to a column-selecting signal that is activated by an address signal. The data bus lines are discharged to the ground potential by a bus-grounding signal BUSG, and are connected to respective bit-line GND sensing circuits BGS by a bus-on signal BUSON.
Each bit-line GND sensing circuit BGS has an inverter amplifier IAMP, a charge-transfer CT, an isolation gate ISO, a threshold voltage generator VTG, a negative voltage generator NEGG, a negative voltage control circuit NEGC, and a coupling capacitor Ctrans for converting a negative voltage to a positive voltage.
Activated by a high level of a short signal SHORT during a read operation, the inverter amplifier IAMP lowers the voltage of the control node VT of the charge-transfer CT (pMOS transistor) when the voltage of the bit line BL or XBL increases.
The threshold voltage generator VTG has a capacitor Cgate that receives the inverted logic of a control signal VTGEN and a clamping circuit that is connected to a node GT. The potential of the node GT is set at −0.7 to 0.7 V by the clamping circuit. The threshold voltage generator VTG generates a negative voltage (−0.7 V) at the node GT in response to a variation of the control signal VTGEN to a high level. This negative voltage is equal to the threshold voltage of the charge-transfer CT.
The negative voltage generator NEGG has a capacitor Ctank that receives the inverted logic of a control signal NEGGEN and a pMOS transistor for initializing a negative-voltage node VNEG to the ground potential. The negative voltage generator NEGG generates a negative voltage at the node VNEG in response to a variation of the control signal NEGGEN to a high level.
The negative voltage control circuit NEGC has capacitors that receive the inverted logic of respective control signals CLP2GEN and CLP1GEN, a pMOS transistor for initializing a node CLP2 to the ground potential, and a clamping circuit that is connected to a node CLP1. The potential of the node CLP1 is set at a value in a range of −2.1 to 0.7 V by the clamping circuit. The node CLP2 is initialized reliably to the ground potential when the potential of the node CLP1 is set at −2.1 V. The negative voltage control circuit NEGC supplies a negative voltage to the control gate of the isolation gate ISO (pMOS transistor) in response to a variation of the control signal CLP2GEN to a high level. As a result, a negative voltage (−0.7 V) of the node GT is transmitted reliably to the node VT when the isolation gate ISO is turned on.
The above-described conventional bit-line GND sensing circuit BGS operates in the following manner and thereby performs a read operation.
First, the control signal CLP1GEN varies to the high level two times, whereby the node CLP2 is initialized to the ground potential. The bit lines BL and XBL are connected to the bit-line GND sensing circuits BGS because the bus-on signal BUSON varies to the high level. The inverter amplifier IAMP is activated because the short signal SHORT varies to the high level.
Then, the potential of the node CLP2 is changed to a negative voltage because the control signal CLP2GEN varies to the high level, whereupon the isolation gate ISO is turned on. The potentials of the nodes GT and VT are changed to −0.7 V because the control signal VTGEN varies to the high level.
The ferroelectric capacitors FC are connected to the respective bit lines BL and XBL because the potential of the word line WL varies to the high level. The bit lines BL and XBL are connected to the respective data bus lines because the column-selecting signal CL varies to the high level. The precharging period of the bit lines BL and XBL and the data bus lines is finished when the bus-grounding signal varies to the low level.
Subsequently, the control signal NEGGEN varies to the high level, whereby the potential of the node VNEG is changed to a negative voltage. Then, the potential of the plate line PL varies to the high level, whereupon the potentials of the bit lines BL and XBL increase in accordance with the residual dielectric polarization values of the ferroelectric capacitors FC, respectively, and, in turn, the potential of the node VT decreases because of the feedback action of the inverter amplifier IAMP. As a result, the charge on each of the bit lines BL and XBL is absorbed by the capacitor Ctank of the negative voltage generator NEGG. That is, the potentials of the bit lines BL and XBL return to the ground potential.
The residual dielectric polarization value of each ferroelectric capacitor FC appears as a voltage variation at the node VNEG that is connected to the capacitor Ctank. The (negative) voltage of the node VNEG is converted to a positive voltage by the coupling capacitor Ctrans. A sense amplifier SA differentially amplifies voltages that are output from the bit-line GND sensing circuits BGS corresponding to the respective bit lines BL and XBL That is, the data that is held by the memory cell MC is read out to the outside.
To keep the potentials of the bit lines BL and XBL during a read operation, the above-described bit-line GND sensing circuits BGS each require the inverter amplifier IAMP, which is a factor of increasing the circuit area. The inverter amplifier IAMP has an operation current of about 100 μA. Ferroelectric memories using 2T2C cells require two bit-line GND sensing circuits for each I/O bit. For example, a ferroelectric memory having a 16-bit data terminal requires 32 bit-line GND sensing circuits BGS. Therefore, the circuit area and the current consumption of each inverter amplifier IAMP have great influences on the chip size and the power consumption, respectively, of a ferroelectric memory.
Further, to enable correct operation of the inverter amplifier IAMP, the isolation gate ISO for isolating the nodes VT and GT from each other is necessary. To transmit a negative voltage generated at the node GT to the node VT via the isolation gate ISO, it is necessary to apply a deep negative voltage to the isolation gate ISO. This requires the complex negative voltage control circuit NEGC. To cause the complex negative voltage control circuit NEGC to operate at the initial stage of a read operation, the node VT potential setting period (precharging period) needs to be sufficiently long (about 30 ns). And the long precharging period is an obstruction to shortening of the read access time.